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10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE802.3 specification.
Support Auto-negotiation.Automatic 32-bit FCS generation and checking.
FCS removal.Programmable inter-packet gap(IPG).
Preamble generation and removal.
Flow control and automatic generation of control frames (pause frame).
Automatic padding short frame on transmitting.
Error status counters.
User interface with internal FIFO.
-Full MAC layer and Reconciliation sub-layerimplementation compliant with IEEE802.3ae specification.
–Passed UNH MAC, Flow-Control, Reconciliation and InterOperability tests
– Standard preamble and SFD (Start of Frame delimiter)insertion and deletion with optional insertion of a user specific 8-Byte preamble
–Lane, data alignment, PHY error and local/remote fault signaling handled by the Core’s Reconciliation sub-layer
– Optional MAC address comparison on receive and overwrite on transmit for NIC applications with programmable promiscuous mode operation
–Optional automatic Pause Frame generation from programmable FIFO congestion thresholds or by dedicated command pin with programmable Quanta
–Programmable frame maximum length providing support for any frame (e.g. Jumbo Frame or any tagged Frame)
–Dynamic inter packet gap (IPG) calculation
–Deficit Idle Counter (DIC) for optimized performance with minimum IPG for LAN applications
–Clock and data rate decoupling with programmable asynchronous FIFOs
-Preamble and SFD (Start of Frame delimiter) insertion and deletion
-Supports up to DDR3-2133 (1066 Mhz DDR interface).
-64 bit DRAM interface (72 bits with ECC); 8 bit ECC calculated across 64 bits of data.
-Single channel support per memory controller. (Requires two separate memory controllers for two channel support)
-Support for 8 Ranks / Chip Selects and 8 output clocks per MCU, using x4, x8, x16 memory modules
-Support for Self-refresh / Auto-refresh
-Auto ZQ calibration (DDR3 only) for PVT variation
-Optimized bank command scheduling for efficient use of DRAM bandwidth. Multi-level queuing and scheduling architecture to reduce DRAM latency and maximize overall bus utilization.
-Support for two Read request priorities and one Write request priority.
-Support for upper limit on latency for each Read / Write priority.
-Programmable address bit mapping from normalized system address (i.e. system address as modified [nomrmalized] by MCB and presented to the MCU) to memory address domain. Multiple address mappings selectable through configuration register.
-DRAM parameters programmable through CSR (Control and Status Register) access
-Total support for 16GB to 64GB of address space per controller
-Open Page Policy with feature to dynamically close pages during DRAM bank management.
-Closed Page Policy with feature to dynamically leave open pages during DRAM bank management.
-Read Leveling and Write Leveling logic to support DQ data eye training. DQS gate enable support.
-Support for DFI Interface Spec, version 2.0 (DDR PHY Interface Standard)
- AMBA® AXI-4 Compatible
- Multiple AXI Channels
- Off the shelf core supports 4 Masters and 8 Slaves
- Arbitration is done at each slave
- Other configurations are available
- Verilog Source
- Complete Test Environment
- AXI Bus Functional Model
-AXI interface is based on the AXI4-Lite specification
– Configurable number of (up to 32) interrupt inputs
– Single interrupt output
– Easily cascaded to provide additional interrupt inputs
– Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority
– Interrupt Enable Register for selectively enabling individual interrupt inputs
– Master Enable Register for enabling interrupt request output
– Each input is configurable for edge or level sensitivity:
– Edge sensitivity can be configured for rising or falling
– Level sensitivity can be active High or active Low
– Output interrupt request pin is configurable for edge or level generation