IC Design

design and verification

AXI Interrupt Controller IP

Design Features.

-AXI interface is based on the AXI4-Lite specification
– Configurable number of (up to 32) interrupt inputs
– Single interrupt output
– Easily cascaded to provide additional interrupt inputs
– Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority
– Interrupt Enable Register for selectively enabling individual interrupt inputs
– Master Enable Register for enabling interrupt request output
– Each input is configurable for edge or level sensitivity:
– Edge sensitivity can be configured for rising or falling
– Level sensitivity can be active High or active Low

– Output interrupt request pin is configurable for edge or level generation


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