IC Design

design and verification

AXI4 DDR3 Memory Controller IP

-Supports up to DDR3-2133 (1066 Mhz DDR interface).

-64 bit DRAM interface (72 bits with ECC); 8 bit ECC calculated across 64 bits of data.

-Single channel support per memory controller. (Requires two separate memory controllers for two  channel support)

-Support for 8 Ranks / Chip Selects and 8 output clocks per MCU, using x4, x8, x16 memory modules

-Support for Self-refresh / Auto-refresh

-Auto ZQ calibration (DDR3 only) for PVT variation

-Optimized bank command scheduling for efficient use of DRAM bandwidth. Multi-level queuing and scheduling architecture to reduce DRAM latency and maximize overall bus utilization.

-Support for two Read request priorities and one Write request priority.

-Support for upper limit on latency for each Read / Write priority.

-Programmable address bit mapping from normalized system address (i.e. system address as modified [nomrmalized] by MCB and presented to the MCU) to memory address domain. Multiple address mappings selectable through configuration register.

-DRAM parameters programmable through CSR (Control and Status Register) access

-Total support for 16GB to 64GB of address space per controller

-Open Page Policy with feature to dynamically close pages during DRAM bank management.

-Closed Page Policy with feature to dynamically leave open pages during DRAM bank management.

-Read Leveling and Write Leveling logic to support DQ data eye training. DQS gate enable support.

-Support for DFI Interface Spec, version 2.0 (DDR PHY Interface Standard)


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