IC Design

design and verification

AXI4 stream 10 Gigabit Ethernet MAC Core

Features :

-Full MAC layer and Reconciliation sub-layerimplementation compliant with IEEE802.3ae specification.

Passed UNH MAC, Flow-Control, Reconciliation and InterOperability tests

Standard preamble and SFD (Start of Frame delimiter)insertion and deletion with optional insertion of a user specific 8-Byte preamble

Lane, data alignment, PHY error and local/remote fault signaling handled by the Core’s Reconciliation sub-layer

Optional MAC address comparison on receive and overwrite on transmit for NIC applications with programmable promiscuous mode operation

Optional automatic Pause Frame generation from programmable FIFO congestion thresholds or by dedicated command pin with programmable Quanta

Programmable frame maximum length providing support for any frame (e.g. Jumbo Frame or any tagged Frame)

Dynamic inter packet gap (IPG) calculation

Deficit Idle Counter (DIC) for optimized performance with minimum IPG for LAN applications

Clock and data rate decoupling with programmable asynchronous FIFOs

-Preamble and SFD (Start of Frame delimiter) insertion and deletion

 

 

 

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