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[ISSCC 2018 Short Course] Introduction to Deep Learning and Inference: A Hardware Perspective

http://www.mediafire.com/file/mjzg740tqfa3wm4/ISSCC_2018_Short_Course_Introduction_to_Deep_Learning_and_Inference_A_Hardware_Perspective.pdf/file

 

[PHD Thesis] High-Performance Decimal Floating-Point Units

http://www.mediafire.com/file/wbxb4778nm9vx7b/%255B1_High_performance_decimal_floating_point_unit.pdf/file

 

ISSCC 2018 T3 Visuals Basics of Quantum Computing

http://www.mediafire.com/file/5icvej9wozfs98u/ISSCC_2018_T3Visuals_Basics_of_Quantum_Computing.pdf/file

 

ISSCC 2018 T10 Visuals ADC-Based Serial Links Design and Analysis

http://www.mediafire.com/file/7n29ldv7e8j1m99/ISSCC_2018_T10_Visuals_ADC-Based_Serial_Links_Design_and_Analysis.pdf/file

ISSCC 2018 T1 Visuals Low-Jitter PLLs for Wireless Transceivers

http://www.mediafire.com/file/k9l277dfukbr9k/ISSCC_2018_T1_Visuals_Low-Jitter_PLLs_for_Wireless_Transceivers.pdf/file

[Book] A Practical Guide to Adopting the Universal Verification Methodology (UVM)

29

http://www.mediafire.com/file/afvzczzg8ck2cb9/%255Ba_practical_guide_to_adopting_the_universal_verfication_methodology.pdf/file

Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification

http://www.mediafire.com/file/umi1l7xylun9fb3/2013-SNUG-SV_Synthesizable-SystemVerilog_presentation.pdf/file

 

[DVCON 2014 Tutorial] Easier UVM – Making Verification Methodology More Productive

http://www.mediafire.com/file/m6mgnnqnmdpaode/T07_Easier_UVM_%25E2%2580%2593_Making_Verification_Methodology_More_Productive.pdf/file

 

Introduction to SystemVerilog for Testbench

http://www.mediafire.com/file/47l58t9fwp923l3/%255BSystemVerilog-Testbench.pdf/file

 

[PHD Thesis] ENERGY EFFICIENT FLOATING-POINT UNIT DESIGN

http://www.mediafire.com/file/u9b03d7bdb7qcnj/%255BENERGY_EFFICIENT_FLOATING-POINT_UNIT_DESIGN.pdf/file