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Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification

http://www.mediafire.com/file/umi1l7xylun9fb3/2013-SNUG-SV_Synthesizable-SystemVerilog_presentation.pdf/file

 

[DVCON 2014 Tutorial] Easier UVM – Making Verification Methodology More Productive

http://www.mediafire.com/file/m6mgnnqnmdpaode/T07_Easier_UVM_%25E2%2580%2593_Making_Verification_Methodology_More_Productive.pdf/file

 

Introduction to SystemVerilog for Testbench

http://www.mediafire.com/file/47l58t9fwp923l3/%255BSystemVerilog-Testbench.pdf/file

 

[PHD Thesis] ENERGY EFFICIENT FLOATING-POINT UNIT DESIGN

http://www.mediafire.com/file/u9b03d7bdb7qcnj/%255BENERGY_EFFICIENT_FLOATING-POINT_UNIT_DESIGN.pdf/file

Synopsis AHB-Based DMA controller manual

http://www.mediafire.com/file/i00r1gs1e3gtngi/%25Bdw_ahb_dmac_db.pdf/file

Advanced UVM Courses

http://www.mediafire.com/file/om4iiki8lh9k20z/UVM_Advanced_Course.rar

[ISSCC 2018 Short Course] Efficient Alternatives and Extensions to Deep-Learning Solutions

http://www.mediafire.com/file/8d3yhl01la3nb62/ISSCC_Short_Course_Efficient_Alternatives_and_Extensions_to_Deep-Learning_Solutions.pdf/file

 

[ISSCC 2018 Short Course] Efficient Edge Solutions for Deep Learning Applications

http://www.mediafire.com/file/ybmgwz5565dcgg7/ISSCC_2018_Short_Course_Efficient_Edge_Solutions_for_Deep_Learning_Applications.pdf/file

[ISSCC 2018 Short Course] Algorithm and Implementation Co-Design for Learning and Inference

http://www.mediafire.com/file/mg44e7b71h55bej/ISSCC_2018_Short_Course_Algorithm_and_Implementation_Co-Design_for_Learning_and_Inference.pdf/file

 

[ISSCC 2018 Short Course] Introduction to Deep Learning and Inference A Hardware Perspective

http://www.mediafire.com/file/23tis8tt0is0ogr/ISSCC_2018_Short_Course_Introduction_to_Deep_Learning_and_Inference_A_Hardware_Perspective.pdf/file