IC Design

design and verification

IP DESIGN

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H.265 Encoder IP

  • HEVC/H.265 Main Profile
  • YUV 4:2:0
  • Bitdepth 8
  • 4K@30fps, 400MHz
  • GOP: I/P
  • CU: 8×8~64×64
  • PU: 4×4~64×64
  • TU: 4×4/8×8/16×16/32×32
  • 1/4 Sub-pixel
  • Search range 32
  • All 35 Intra prediction mode
  • CABAC
  • Deblocking Filter
  • SAO
  • Rate control: CBR/VBR (Software)

http://www.mediafire.com/file/pund39n5d45u086/h265_encoder.rar/file

Free RTL and Verilog Testbench of SPI Wishbone Controller

24

http://www.mediafire.com/file/71ste4a9v5skzlb/spi_wb_master_lattice.rar

openHMC Controller

Open Silicon HMC Memory Controller IP.gif

https://ra.ziti.uni-heidelberg.de/cag/research/recent-research-projects/openhmc