IC Design

design and verification


now browsing by category


10/100Mb/s Ethernet IP Core

Design Features.

– Performing MAC layer functions of IEEE 802.3.

– Automatic 32-bit CRC generation and checking.

– AXI4 Slave interface.

– Supports MDIO.

– 4KB SRAM Ping-pong TX buffer.

– 4KB SRAM Ping-pong RX buffer.

– Receive and Transmit Interrupts.

– Automatically pad short frames on transmit.

– Collision detection and auto retransmission on collisions in half duplex mode (CSMA/CD protocol).

– Loopback mode.

AXI4-based CAN controller

Features :

-Conforms to the CAN 2.0A, and CAN2.0B standards.

-Support both standard (11-bit identifier) and extended (29-bit identifier) frames.

-Up to 1 Mbps.

-Transmit message FIFO supports up to 64 messages.

-Receive message FIFO supports up to 64 messages.

-Support up to 4 ID filters.

-Sleep Mode with automatic wake-up.

-Loop Back Mode for diagnostic applications.

-Interrupts, status, error counters.

-Support 32 bits APB interface.

AXI SPI Mater Controller Features

-8 bit, 16 bit, 24 bit, and 32 bit synchronous serial transmission

-Full duplex operation

-Software programmable Master or Slave mode

-Software programmable SCLK rate

-16 word/byte Transmit FIFO (configuration option)

-16 word/byte Receive FIFO (configuration option)

-AMBA AXI4 Lite interface

-LSB or MSB mode

-Up to 4 slaves under Master control

-Data rate up to 40 Mb/s



ASIC/FPGA Design Services

We provide a wide variety of IP designs (I2C, USB, DDR2/3 Controller, Ethernet MAC, RISC-V processor, CAN, CANFD, AHB/AXI interconnect …) and services including design specification, RTL coding, Verification, FPGA prototyping, Synthesis ….